Creating a Unit Test Template

New unit test templates are created using create_unit_test.pl. Usage of create_unit_test.pl is as follows:

Usage:  create_unit_test.pl [ -help | -uvm | -out <file> | -overwrite | uut.sv ]

Where -help                : prints this help screen
      -uvm                 : generate a uvm component test template
                             IMPORTANT: do not use '-uvm' unless the UUT is derived from a uvm_component
      -out <file>          : specifies a new default output file
      -overwrite           : overwrites the output file if it already exists
      -class_name <name>   : generate a unit test template for a class <name>
      -module_name <name>  : generate a unit test template for a module <name>
      -if_name <name>      : generate a unit test template for an interface <name>
      uut.sv               : the file with the unit under test

A template can be generated by using any of the -class_name, -module_name, -if_name switches or by specifying a verilog file that contains a definition of the UUT. For example, you can generate a new unit test template for a class called ‘foo’ with:

create_unit_test.pl -class_name foo

Likewise, if you already have a definition for class ‘foo’ in ‘foo.v’, you can generate a corresponding unit test template with:

create_unit_test.pl foo.v

The default output for create_unit_test.pl is written to ./<name>_unit_test.sv. The default can be overridden, however, using the -out <file> switch. A different file name and/or directory can be specified as required. The file name, however, must follow the <name>_unit_test.sv format.

Existing files will not be overwritten unless the -overwrite switch is used.

Integrating the UUT

The template generated by create_unit_test.pl includes an instance of the UUT as well as other important parts of the infrastructure. The UUT does not, however, include any pin level connectivity so connectivity is handled by users. For example, if a template is created for a module named ‘test_module’, an instance of ‘test_module’ is created as:

//===================================
// This is the UUT that we're
// running the Unit Tests on
//===================================
test_module my_test_module();

If test_module has two outputs, oBus and oPin, and one input, iPin, a user connects them as normal Verilog IO thereby making them accessible within the unit test template:

//===================================
// This is the UUT that we're
// running the Unit Tests on
//===================================
reg        iPin;
wire [7:0] oBus;
wire       oPin;
test_module my_test_module(.iPin(iPin),
                           .oBus(oBus),
                           .oPin(oPin));