Welcome to SVUnit’s documentation!

SVUnit is a simple, well-structured verification framework intended for design and verification engineers writing and running tests against Verilog modules, classes or interfaces. By first verifying the individual pieces of a design or testbench in isolation, we can assume much higher quality of the design or testbench as a whole. The feature characteristic of SVUnit is ease-of-use, meaning developers can be up-and-running in an hour or less. SVUnit is open-source under Apache 2.0 licensing making it accessible and productive for any engineer with a Verilog simulator.

Contents

• Structure and Workflow
• Installation and Setup
• Creating a Unit Test Template
  • Integrating the UUT
• Writing Unit Tests
  • SVUnit Reporting Macros
  • Setting Test Exit Status
  • Interacting with the UUT
  • Test Setup and Teardown
• Special Considerations for Unit Testing UVM Components
• Running Unit Tests
  • Choosing a Simulator
  • Logging
  • Specifying Command-line Macros
  • Adding Files For Simulation
  • Adding Run Time and/or Compile and/or Elaboration Options
  • Enable UVM Component Unit Testing
  • Specifying a Simulation Directory
  • Specifying Unit Tests to be Run
  • Listing Test Names
• Simulator Output
• Support and More Information
• User Guide Feedback